C4.1 - A Programmable 7GHz Frequency Divider in a SiGe Bipolar Technology for Highly Linear Fractional-N Ramp Generation
- SENSOR+TEST Conferences 2011
2011-06-07 - 2011-06-09
- Proceedings SENSOR 2011
- C4 - Sensor Electronic I
- G. Hasenäcker, N. Pohl, T. Musch - Ruhr-Universität Bochum (Germany), H. Knapp - Infineon Technologies AG, Neubiberg (Germany)
- 429 - 432
Millimeter wave radar systems are well suited for applications in automotive and industrial distance measurement sensors. The precision of FMCW radar systems notably depends on the bandwidth and the linearity of the generated frequency ramps. Thus, high precision and high speed measurement systems are in need of highly linear frequency ramps.
The realization requires a phase-locked loop (PLL) with an adjustable output frequency. The PLL’s output frequency is determined by the division ratio of a frequency divider in the loop. Distinct improvement in linearity and noise is achieved by fractional synthesizers. These require high speed programmable dividers and fast switching of the division ratio in a wide range. For the best noise performance the system should be designed for low division ratios and thus a high reference frequency.
This paper presents a programmable frequency divider operating up to 7 GHz for division ratios between 12 and 255. The divider is realized with a dual-modulus prescaler and two programmable dividers handling the signal at the prescaler output. The presented circuit is implemented in Infineon’s 0.35 μm high frequency SiGe bipolar technology (fT=200 GHz, fmax=250 GHz) and uses completely differential current mode logic, which serves for high speed and high reliability.
A further advantage of using a high speed bipolar technology is the possibility to integrate other RF components such as a voltage controlled oscillator (VCO) on the same chip. Hence, the complete circuit gives a cost, area and power efficient solution for usage in high speed phase-locked-loops for e.g. millimeter-wave FMCW radar systems.
The circuit is optimized for low power while meeting the requirements for the application in a high frequency PLL. The divider operates at a supply voltage of 3.3 V at a total power consumption of 130 mW including output drivers and a logic interface for programming the division ratio.