4.1 - Hardware Acceleration for Beamforming Algorithms based on Optimized Hardware-/Software Partitioning

ettc2018 - European Test and Telemetry Conference
2018-06-26 - 2018-06-28
Nürnberg, Germany
4. RF Design
R. Schmidt, S. Blokzyl, W. Hardt - Technische Universität Chemnitz (Germany)
78 - 86


Beamforming techniques are widely used in many fields of research like sonar, radar, wireless communication and speech processing applications. Beamforming algorithms are mainly used for signal enhancement and direction of arrival estimation. In applications for tracking mobile communication partners like speaker or aircrafts, beamforming algorithms are employed to estimate the direction of arrival.
Beamforming processing is always accompanied by high computational costs, which are challenging for embedded devices. Recent approaches process the calculation in frequency domain to reduce the processing time. However, in many cases the processing is still very slow and cannot be used for realtime processing. Alternative real-time solutions based on FPGAs face the drawback of long development processes and restricted communication interfaces.
This paper introduces a novel implementation approach based on System on Chip (SoC) technology with optimized Hardware-/Software Partitioning for real-time delay and sum beamforming. Basis for evaluation is a runtime measurement of software implementations to determine computation steps with high processing time and parallelization capabilities. Extracted computation steps are implemented on an associated FPGA with full pipelined architecture for high data throughput and fast processing speed. The complexity of the deduced architecture is evaluated regarding data length and data width with respect to computational accuracy.