D5.3 - Electrical Characterization of the SiO2/4H-SiC Interface
- Event
- SMSI 2023
2023-05-08 - 2023-05-11
Nürnberg - Band
- Lectures
- Chapter
- D5 - Metrology of compound semiconductors for manufacturing power electronics
- Author(s)
- C. Nanjappan, G. Pfusterschmied, U. Schmid - Technische Universität Wien, Vienna (Austria)
- Pages
- 235 - 236
- DOI
- 10.5162/SMSI2023/D5.3
- ISBN
- 978-3-9819376-8-8
- Price
- free
Abstract
The interface trap density Dit is an important parameter to characterize the quality of the oxide/semicon-ductor interface. The low channel mobility (20 cm2/Vs for dry thermal oxidation) in silicon carbide-based MOS devices is mostly attributed to the high amount of interface traps. To attain high mobilities (>80 cm2/Vs), it is required to reduce the Dit to the range of 1010 cm-2eV-1 or below. Post oxidation annealing under nitrogen-based gaseous environment is known to reduce Dit, but still there is the requirement to reduce the Dit to reach those values of standard silicon/silicon-dioxide interfaces (1010 – 1011 cm-2eV-1). Oxides on SiC formed by plasma oxidation process instead of dry oxidation represents a promising technology, as it is known for exhibiting lower Dit values in the range of 1010 – 1011 cm-2eV-1. However, the physics behind the plasma oxidation of 4H-SiC is not yet completely understood. In this work, we report first results about the enhanced oxidation rate and improved electrical characteristics when an oxygen plasma pre-treatment is implemented before the standard dry oxidation of 4H-SiC.